Voltage divider bias

Posted by AJ × 01:39

This is the biasing circuit wherein, ICQ and VCEQ are almost independent of β.

The level of IBQ will change with β so as to maintain the values of ICQ and VCEQ almost

same, thus maintaining the stability of Q point.

Two methods of analyzing a voltage divider bias circuit are:

Exact method – can be applied to any voltage divider circuit

Approximate method – direct method, saves time and energy, can be applied in most of

the circuits.

Exact method

In this method, the Thevenin equivalent network for the network to the left of the base

terminal to be found.

To find Rth:

From the above circuit,

Rth = R1|| R2

= R1 R2 / (R1 + R2)

To find Eth

From the above circuit,

Eth = VR2 = R2VCC / (R1 + R2)

In the above network, applying KVL

( Eth – VBE) = IB [ Rth +( β + 1) RE ]

IB = ( Eth – VBE) / [ Rth +( β + 1) RE ]

Analysis of Output loop

KVL to the output loop:

VCC = ICRC + VCE + IERE

IE ~= IC

Thus, VCE = VCC – IC (RC + RE)

Note that this is similar to emitter bias circuit.

All Syllabus